1. Field of the Invention
The present invention relates to an equalizer circuit for interconnecting an electrical signal, and a printed circuit board installed with the equalizer circuit.
2. Background Art
In recent years, as the performance of electronic instruments increases, the signal interconnection speed between electronic components such as LSI (Large Scale Integration) circuits installed in an electronic instrument has been approximately doubling every three years. Particularly, in a backplane used in large-volume data processing equipment such as a server and a rooter, etc., it is predicted that an interconnection speed of more than 25 Gbps which means a limit of electrical interconnection will be demanded in about the year of 2012.
As the interconnection speed increases, the insertion loss in a printed board wiring increases resulting in an increase in the difference in group delay associated with the change of frequency. Such an insertion loss and the difference in group delay will increase jitter in the signal waveform. This may cause a shortening of the distance over which interconnection is possible or an increase of the bit error rate of interconnection information. Accordingly, it is necessary to smooth the frequency characteristics of the insertion loss and the group delay of the printed board wiring, thereby reducing jitter in the signal waveform.
JP Patent Publication (Kokai) No. 2003-309461 describes a technique for superimposing an emphasis signal for enhancing higher frequency components on a transmission signal. JP Patent Publication (Kokai) No. 5-83164 (1993) describes a technique for smoothing the frequency characteristic of a board wiring by equipping an equalizer circuit in the reception circuit.
JP Patent Publications (Kokai) No. 2006-254303 and No. 2008-294837 disclose a technique for smoothing the frequency characteristic of a printed board wiring by making up an equalizer circuit using passive components (a passive equalizer) to reduce power consumption.